module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);

    reg	[3:0] out_reg;
    
    assign out = out_reg[3];
    
    always @(posedge clk) begin
        if(!resetn) begin
            out_reg <= 4'd0;
        end
        else begin
            out_reg <= {out_reg[2:0], in};
        end
    end
    
endmodule
